Key Responsibility (主要职责)：

• The front-end/back-end verification of IC projects, mainly focusing on mixed-signal chip level verification;
• Verification planning, review, and architecture definition;
• Development and implementation of verification test benches;
• Development of verification components, using in UVM and other mainstream verification methodology;
• Development of direct and constrained
• Random stimulus, and understanding functional and assertion coverage results;
• Identifying cost-effective and innovative verification techniques;
• Experience with assertion-based verification and automated test case/scenario generation (e.g., Perspec) is a plus.