Principal Verification Engineer - Team Lead (d/m/f)
Valencia, Valencian Community, Spain – ams R&D Spain S.L.
What we expect
- Verification of mixed-signal CMOS ICs and IP blocks
- Define verification plans for mixed-signal circuits and ensure adequate verification coverage to enable bug free silicon manufacturing
- Model analog and mixed-signal blocks using a high-level description language (e.g. SystemVerilog, VerilogAMS)
- Create DV (Design Verification) test cases, run associated simulations and debug the results
- Lead and mentor less experienced DV engineers
- Promote cutting-edge DV methodologies and make their use available to the community
Who we are looking for
- Successfully completed university degree in Electronics, Electrical Engineering, Physics or comparable
- Several years (~7 years) of professional experience in mixed-signal design/verification with hands-on experience with relevant design/simulation tools
- Solid knowledge of design verification methods, tools and languages (Digital Mixed-Signal simulation, SystemVerilog, UVM, assertions …)
- Experience in analog block modeling
- Analytical mind to solve complex problems and debugging skills
- Team-oriented and ability to mentor less experienced engineers
- Strong commitment to deadlines and the advancement of the DV discipline
- Good communication skills and proficiency in English
Contact
Stefanie Kleierl will be happy to answer any questions you may have.
Phone: +49 941 850 1391
E-Mail: stefanie.kleierl@ams-osram.com
For data protection reasons, we only accept applications submitted through our applicant portal. This allows you to view the status of your application in your profile at any time.
Job details
Posting date: | 2024/09/24 |
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Experience level: | Professional (> 3 Years) |
Type of contract: | Permanent |
Employment type: | Full-time |
Work Model: | Hybrid 25 % |
Business unit: | CMOS Sensors & ASICs |
Organization: | ams R&D Spain S.L. |
Job field: | Research & Development |
Job ID: | 19092 |