你的职责
- Develop testbenches using System Verilog and UVM for functional and power aware RTL
- Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage.
- Develop test plan, UVM based test sequences, layered sequences, virtual sequencers
- Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware and Gate level timing simulation.
- Provide regression setup, debug of RTL and gate level netlist
- Review industry standard spec and augment test plan to improve quality of verification
- Participate in post silicon bring up, validation and compliance testing and debug
- Work collaboratively with cross-functional teams like product Architect, Designers, firmware development team to ensure successful delivery of product
