Senior Staff Engineer, RD Digital Verification
海得拉巴, 特伦甘地, 印度 – ams Semiconductors India
职位要求
- Develop testbenches using System Verilog and UVM for functional and power aware RTL
- Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage.
- Develop test plan, UVM based test sequences, layered sequences, virtual sequencers
- Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware and Gate level timing simulation.
- Develop ‘C’ testcases for HW-FW simulation and FPGA prototyping
- Provide regression setup, debug of RTL and gate level netlist
- Review industry standard spec and augment test plan to improve quality of verification
- Participate in post silicon bring up, validation and compliance testing and debug
- Work collaboratively with cross-functional teams like product Architect, Designers, firmware development team to ensure successful delivery of product
联系我们
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工作细节
| 发布日期: | 2025/06/30 |
|---|---|
| 经验水平: | 经验丰富的专业人士（> 8年） |
| 合同类型: | 正式 |
| 时间安排: | 全职 |
| 工作模式: | 混合 |
| 业务单元: | CMOS Sensors & ASICs |
| 组织: | ams Semiconductors India |
| 工作领域: | 研发 |
| 工作编号: | 20518 |
