Principal Verification Engineer - Team Lead (d/m/f)
巴伦西亚, 瓦伦西亚, 西班牙 – ams R&D Spain S.L.
职位要求
- Verification of mixed-signal CMOS ICs and IP blocks
- Define verification plans for mixed-signal circuits and ensure adequate verification coverage to enable bug free silicon manufacturing
- Model analog and mixed-signal blocks using a high-level description language (e.g. SystemVerilog, VerilogAMS)
- Create DV (Design Verification) test cases, run associated simulations and debug the results
- Lead and mentor less experienced DV engineers
- Promote cutting-edge DV methodologies and make their use available to the community
联系我们
Stefanie Kleierl 将很乐意回答您的任何问题。
电话: +49 941 850 1391
电子邮件地址: stefanie.kleierl@ams-osram.com
出于信息保护的原因，我们仅接受官方岗位申请渠道的申请投递。您也可以通过岗位主页查询您的申请进度。
工作细节
| 发布日期: | 2024/09/24 |
|---|---|
| 经验水平: | 专业（> 3年) |
| 合同类型: | 正式 |
| 时间安排: | 全职 |
| 工作模式: | 混合动力 25 |
| 业务单元: | CMOS Sensors & ASICs |
| 组织: | ams R&D Spain S.L. |
| 工作领域: | 研发 |
| 工作编号: | 19092 |
